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| hexfet power mosfet s d g benefits improved gate, avalanche and dynamic dv/dt ruggedness fully characterized capacitance and avalanche soa enhanced body diode dv/dt and di/dt capability lead-free applications high efficiency synchronous rectification in smps uninterruptible power supply high speed power switching hard switched and high frequency circuits gds gate drain source v dss 24v r ds(on) typ. 0.8m max. 1.0m i d (silicon limited) 429a i d (package limited) 240a absolute maximum ratings symbol parameter units i d @ t c = 25c continuous drain current, v gs @ 10v (silicon limited) a i d @ t c = 100c continuous drain current, vgs @ 10v (silicon limited) i d @ t c = 25c continuous drain current, v gs @ 10v (package limited) i dm pulsed drain current p d @t c = 25c maximum power dissipation w linear derating factor w/c v gs gate-to-source voltage v dv/dt peak diode recovery v/ns t j operating junction and c t stg storage temperature range soldering temperature, for 10 seconds avalanche characteristics e as (thermally limited) single pulse avalanche energy mj i ar avalanche current a e ar repetitive avalanche energy mj thermal resistance symbol parameter typ. max. units r jc junction-to-case CCC 0.50 c/w r ja junction-to-ambient (pcb mount) , d 2 pak CCC 40 230 see fig. 14, 15, 22a, 22b, 300 1.6 -55 to + 175 20 2.0 300 (1.6mm from case) max. 429 303 1640 240 !"# form quantity tube 50 irf1324s-7ppbf tape and reel left 800 IRF1324STRL-7PP base part number package type standard pack irf1324s-7ppbf d 2 pak-7pin orderable part number downloaded from: http:/// !"# calculated continuous current based on maximum allowable junction temperature. package limitation current is 240a. note that current limitations arising from heating of the device leads may occur withsome lead mounting arrangements. http://www.irf.com/technical-info/appnotes/an-1140.pdf repetitive rating; pulse width limited by max. junction temperature. limited by t jmax , starting t j = 25c, l = 0.018mh r g = 25 , i as = 160a, v gs =10v. part not recommended for use above this value. s d g i sd 160a, di/dt 600a/ s, v dd v (br)dss , t j 175c. pulse width 400 s; duty cycle 2%. c oss eff. (tr) is a fixed capacitance that gives the same charging time as c oss while v ds is rising from 0 to 80% v dss . c oss eff. (er) is a fixed capacitance that gives the same energy as c oss while v ds is rising from 0 to 80% v dss . when mounted on 1" square pcb (fr-4 or g-10 material). for recom mended footprint and soldering techniques refer to application note #an-994. !" static @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units v (br)dss drain-to-source breakdown voltage 24 CCC CCC v ? v (br)dss / ? t j breakdown voltage temp. coefficient CCC 0.023 CCC v/c r ds(on) static drain-to-source on-resistance CCC 0.80 1.0 m v gs(th) gate threshold voltage 2.0 CCC 4.0 v i dss drain-to-source leakage current CCC CCC 20 a CCC CCC 250 i gss gate-to-source forward leakage CCC CCC 200 na gate-to-source reverse leakage CCC CCC -200 r g internal gate resistance CCC 3.0 CCC dynamic @ t j = 25c (unless otherwise specified) symbol parameter min. typ. max. units gfs forward transconductance 270 CCC CCC s q g total gate charge CCC 180 252 nc q gs gate-to-source charge CCC 47 CCC q gd gate-to-drain ("miller") charge CCC 58 CCC q sync total gate charge sync. (q g - q gd ) CCC 122 CCC t d(on) turn-on delay time CCC 19 CCC ns t r rise time CCC 240 CCC t d(off) turn-off delay time CCC 86 CCC t f fall time CCC 93 CCC c iss input capacitance CCC 7700 CCC pf c oss output capacitance CCC 3380 CCC c rss reverse transfer capacitance CCC 1930 CCC c oss eff. (er) effective output capacitance (energy related) CCC 4780 CCC c oss eff. (tr) effective output capacitance (time related) CCC 4970 CCC diode characteristics symbol parameter min. typ. max. units i s continuous source current CCC CCC 429 a (body diode) i sm pulsed source current CCC CCC 1636 a (body diode) v sd diode forward voltage CCC CCC 1.3 v t rr reverse recovery time CCC 71 107 ns t j = 25c v r = 20v, CCC 74 110 t j = 125c i f = 160a q rr reverse recovery charge CCC 83 120 nc t j = 25c di/dt = 100a/ s CCC 92 140 t j = 125c i rrm reverse recovery current CCC 2.0 CCC a t j = 25c t on forward turn-on time intrinsic turn-on time is negligible (turn-on is dominated by ls+ld) conditions v ds = 50v, i d = 160a i d = 75a v gs = 20v v gs = -20v mosfet symbol showing the v ds =12v conditions v gs = 10v v gs = 0v v ds = 19v ? = 1.0mhz, see fig.5 v gs = 0v, v ds = 0v to 19v , see fig.11 v gs = 0v, v ds = 0v to 19v t j = 25c, i s = 160a, v gs = 0v integral reverse p-n junction diode. conditions v gs = 0v, i d = 250 a reference to 25c, i d = 5ma v gs = 10v, i d = 160a v ds = v gs , i d = 250 a v ds = 24v, v gs = 0v v ds = 19v, v gs = 0v, t j = 125c i d = 160a r g =2.7 v gs = 10v v dd = 16v i d = 75a, v ds =0v, v gs = 10v downloaded from: http:/// $ !"# fig 1. typical output characteristics fig 3. typical transfer characteristics fig 4. normalized on-resistance vs. temperature fig 2. typical output characteristics fig 6. typical gate charge vs. gate-to-source voltage fig 5. typical capacitance vs. drain-to-source voltage 2 3 4 5 6 7 8 9 v gs , gate-to-source voltage (v) 0.1 1 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) t j = 25c t j = 175c v ds = 15v 60 s pulse width -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , junction temperature (c) 0.6 0.8 1.0 1.2 1.4 1.6 1.8 r d s ( o n ) , d r a i n - t o - s o u r c e o n r e s i s t a n c e ( n o r m a l i z e d ) i d = 160a v gs = 10v 1 10 100 v ds , drain-to-source voltage (v) 1000 10000 100000 c , c a p a c i t a n c e ( p f ) v gs = 0v, f = 1 mhz c iss = c gs + c gd , c ds shorted c rss = c gd c oss = c ds + c gd c oss c rss c iss 0 50 100 150 200 q g , total gate charge (nc) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 v g s , g a t e - t o - s o u r c e v o l t a g e ( v ) v ds = 19v v ds = 12v i d = 75a 0.1 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) vgs top 15v 10v 8.0v 6.0v 5.5v 5.0v 4.8v bottom 4.5v 60 s pulse width tj = 25c 4.5v 0.1 1 10 100 v ds , drain-to-source voltage (v) 10 100 1000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) 4.5v 60 s pulse width tj = 175c vgs top 15v 10v 8.0v 6.0v 5.5v 5.0v 4.8v bottom 4.5v downloaded from: http:/// !"# fig 8. maximum safe operating area fig 10. drain-to-source breakdown voltage fig 7. typical source-drain diode forward voltage fig 11. typical c oss stored energy fig 9. maximum drain current vs. case temperature fig 12. maximum avalanche energy vs. draincurrent 0.0 0.5 1.0 1.5 2.0 2.5 v sd , source-to-drain voltage (v) 1.0 10 100 1000 i s d , r e v e r s e d r a i n c u r r e n t ( a ) t j = 25c t j = 175c v gs = 0v -5 0 5 10 15 20 25 v ds, drain-to-source voltage (v) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 e n e r g y ( j ) 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 100 200 300 400 500 600 700 800 900 1000 e a s , s i n g l e p u l s e a v a l a n c h e e n e r g y ( m j ) i d top 45a 80a bottom 160a 0 1 10 100 v ds , drain-to-source voltage (v) 1 10 100 1000 10000 i d , d r a i n - t o - s o u r c e c u r r e n t ( a ) operation in this area limited by r ds (on) tc = 25c tj = 175c single pulse 100 sec 1msec 10msec dc -60 -40 -20 0 20 40 60 80 100 120 140 160 180 t j , temperature ( c ) 24 25 26 27 28 29 30 31 32 v ( b r ) d s s , d r a i n - t o - s o u r c e b r e a k d o w n v o l t a g e ( v ) id = 5ma 25 50 75 100 125 150 175 t c , case temperature (c) 0 50 100 150 200 250 300 350 400 450 i d , d r a i n c u r r e n t ( a ) limited by package downloaded from: http:/// % !"# fig 14. typical avalanche current vs.pulsewidth 1.0e-06 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 tav (sec) 1 10 100 1000 a v a l a n c h e c u r r e n t ( a ) 0.05 duty cycle = single pulse 0.10 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? j = 25c and tstart = 150c. 0.01 allowed avalanche current vs avalanche pulsewidth, tav, assuming ? tj = 150c and tstart =25c (single pulse) fig 13. maximum effective transient thermal impedance, junction-to-case 1e-006 1e-005 0.0001 0.001 0.01 0.1 t 1 , rectangular pulse duration (sec) 0.001 0.01 0.1 1 t h e r m a l r e s p o n s e ( z t h j c ) c / w 0.20 0.10 d = 0.50 0.02 0.01 0.05 single pulse ( thermal response ) notes: 1. duty factor d = t1/t2 2. peak tj = p dm x zthjc + tc j j 1 1 2 2 3 3 r 1 r 1 r 2 r 2 r 3 r 3 ci i / ri ci= i / ri c 4 4 r 4 r 4 ri (c/w) i (sec) 0.02070 0.0000100.08624 0.000070 0.24491 0.001406 0.15005 0.009080 downloaded from: http:/// & !"# fig 15. maximum avalanche energy vs. temperature notes on repetitive avalanche curves , figures 14, 15:(for further info, see an-1005 at www.irf.com) 1. avalanche failures assumption: purely a thermal phenomenon and failure occurs at a temperature far inexcess of t jmax . this is validated for every part type. 2. safe operation in avalanche is allowed as long ast jmax is not exceeded. 3. equation below based on circuit and waveforms shown in figures 16a, 16b.4. p d (ave) = average power dissipation per single avalanche pulse. 5. bv = rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. i av = allowable avalanche current. 7. ? t = allowable rise in junction temperature, not to exceed t jmax (assumed as 25c in figure 14, 15).t av = average time in avalanche. d = duty cycle in avalanche = t av f z thjc (d, t av ) = transient thermal resistance, see figures 13) p d (ave) = 1/2 ( 1.3bvi av ) = t/ z thjc i av = 2 t/ [1.3bvz th ] e as (ar) = p d (ave) t av 25 50 75 100 125 150 175 starting t j , junction temperature (c) 0 50 100 150 200 250 e a r , a v a l a n c h e e n e r g y ( m j ) top single pulse bottom 1.0% duty cycle i d = 160a fig 16. threshold voltage vs. temperature -75 -50 -25 0 25 50 75 100 125 150 175 200 t j , temperature ( c ) 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v g s ( t h ) , g a t e t h r e s h o l d v o l t a g e ( v ) i d = 250 a i d = 1.0ma i d = 1.0a downloaded from: http:/// ' !"# fig 23a. switching time test circuit fig 23b. switching time waveforms fig 22b. unclamped inductive waveforms fig 22a. unclamped inductive test circuit fig 24a. gate charge test circuit fig 24b. gate charge waveform fig 21. for n-channel hexfet power mosfets ? ? ? p.w. period di/dt diode recovery dv/dt ripple 5% body diode forward drop re-appliedvoltage reverserecovery current body diode forward current v gs =10v v dd i sd driver gate drive d.u.t. i sd waveform d.u.t. v ds waveform inductor curent d = p. w . period # $%# &'(& ) )( + - + + + - - - # ? ! " ? # $%$$ ? ! & ' ' ? $%$$( % r g i as 0.01 t p d.u.t l v ds + - v dd driver a 15v 20v v gs v dd v ds l d d.u.t + - second pulse width < 1 s duty factor < 0.1% t p v (br)dss i as 1k vcc dut 0 l s 20k vds vgs id vgs(th) qgs1 qgs2 qgd qgodr v gs v ds 90% 10% t d(on) t d(off) t r t f downloaded from: http:/// " !"# d 2 pak - 7 pin package outline dimensions are shown in millimeters (inches) downloaded from: http:/// ( !"# d 2 pak - 7 pin part marking information d 2 pak - 7 pin tape and reel assembly lot code international rectifier logo date code y = year w = week p = leadfree 89 ywwp 17 part number f1324s-7p downloaded from: http:/// !"# http//www.irf.com/ !"" #$$ %& " ' ! !"!! # ! $ $! %!! &''((( )'(%!* ' ms l 1 (per jedec j-std-020d ?? ) rohs c ompliant yes qualification information ? qualification level moisture sensitivity level d 2 pak-7pin industrial ?? (per jedec jesd47f ??? guidelines) date comments ? added odering information table on page 1 ? updated package outline on page 8 ? updated part marking on page 9 ? added qualification table on page 10. ? updated data sheet with new ir corporate template revision history 4/8/2014 downloaded from: http:/// |
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